| Title: | 先進電子設計自動化技術研發-子計畫六：用於奈米晶片系統設計之功率意識高階合成研究(III) Study on Power-aware High-level Synthesis Techniques for Nenometer SOC Design(III) |
| Authors: | 董蘭榮 Dung Lan-Rong 交通大學電機與控制工程系 |
| Issue Date: | 2005 |
| Gov't Doc #: | NSC94-2220-E009-023 |
| URI: | http://hdl.handle.net/11536/90650 https://www.grb.gov.tw/search/planDetail?id=1147284&docId=220348 |
| Appears in Collections: | Research Plans |
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