單晶片系統驗證之核心技術開發-子計畫一：高階合成之形式驗證技術研究

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DC Field	Value	Language
dc.contributor.author	董蘭榮	en_US
dc.contributor.author	Dung Lan-Rong	en_US
dc.date.accessioned	2014-12-13T10:31:07Z	-
dc.date.available	2014-12-13T10:31:07Z	-
dc.date.issued	2005	en_US
dc.identifier.govdoc	NSC94-2220-E009-039	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/90725	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=1147349&docId=220364	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	單晶片系統驗證之核心技術開發-子計畫一：高階合成之形式驗證技術研究	zh_TW
dc.title	Study on Formal Verification for High-Level Synthesis	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電機與控制工程系	zh_TW
Appears in Collections:	Research Plans

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