高性能混合訊號式介面積體電路-子計畫五：低電壓差動信號傳輸接收器之設計與量測(III)

Full metadata record

DC Field	Value	Language
dc.contributor.author	吳錦川	en_US
dc.date.accessioned	2014-12-13T10:31:23Z	-
dc.date.available	2014-12-13T10:31:23Z	-
dc.date.issued	2004	en_US
dc.identifier.govdoc	NSC93-2215-E009-013	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/90898	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=1026642&docId=195164	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	高性能混合訊號式介面積體電路-子計畫五：低電壓差動信號傳輸接收器之設計與量測(III)	zh_TW
dc.title	The Design and Testing of High Performance LVDS Transceiver(III)	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
Appears in Collections:	Research Plans

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