Design of memory sub-system in H.264/AVC decoder

Abstract

In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency; less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.