覆晶式封裝微力感測器之設計、製作及測試(II)

Abstract

本計劃為去年計劃.多晶矽壓阻式微力感測器之設計、製作及測試研究(I).之延伸。在 成功製作出微力感測器後，封裝及對其之可靠測試是最大的挑戰。一般半導體工業用之 封裝技術常無法滿足此一需求，因此針對所製作出之元件，設計一簡單、低成本及高穩 定性的封裝技術是必須的。本計劃旨在將以微機電製程實現之力感測器為基礎，設計一 套完整的微機電覆晶封裝技術來完成此力感測元件封裝，並架設一測試平台以量測其特 性與封裝之可靠度，並驗證所提出之設計及模型。所封裝之力感測器為一以多晶矽作壓 阻之微力感測元件，其設計以圓形之薄膜中心的凸出物作為力之導引結構。計劃初期， 預先模擬分析其封裝應力、熱傳及極限崩壞之分析。中期實際製作將元件封於印刷電路 板上，並架設測試平台。計劃末期，將完成之封裝元件在平台上做實際測試並探討之。 經由此研究計劃，覆晶封裝技術應用於微機電系統趨於可行，將可實際被應用於生產，提 升微機電的應用範疇。

This proposal is continued from the last project have named 「Design, fabrication and testing of poly-Si piezoresistive micro force sensors (I).」 After we successfully fabricated the proposed micro force sensors, the work of reliable package confronts many challenges. Those conventional packages used by semiconductor electronic devices are not satisfied its requirements. Therefore, a simple, low cost and high reliable package to cover our need should be developed. In this proposal, a flip-chip technology is developed to package our fabricated micro force sensors. Than, the packaged sensor will be mounted on a test station to measure its properties and reliability, thus, to prove our design. The packaged sensor is a piezoresistive force sensor which is formed by a circular membrane with a center boss to serve as its force conducting structure. In the primary stage, we propose to undertake some simulations for analyzing the stress, heat conduction, and the failure model of the package. In the middle stage, we will package our devices on a PCB and install our test station. After the package, the characteristic of the device can be measured. During the execution of the project, applying flip-chip package technique to MEMS devices will be studied and will have benefits in the industry.