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dc.contributor.author黃俊達en_US
dc.contributor.authorHuang Juinn-Daren_US
dc.date.accessioned2014-12-13T10:31:42Z-
dc.date.available2014-12-13T10:31:42Z-
dc.date.issued2004en_US
dc.identifier.govdocNSC93-2220-E009-029zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/91118-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1030986&docId=196434en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.titleE-Home核心技術之研究---子計畫五晶片上匯流排之架構設計及效能分析技術(I)zh_TW
dc.titleTechnologies on Architecture Design and Performance Analysis of On-Chip Bus(I)en_US
dc.typePlanen_US
dc.contributor.department交通大學電子工程系zh_TW
Appears in Collections:Research Plans