針對晶片系統連接網路之驗證與自動合成之研究(III)

標題:	針對晶片系統連接網路之驗證與自動合成之研究(III) The Study on Interconnection Verification and Synthesis for SoC(III)
作者:	周景揚 JOU JING-YANG 交通大學電子工程系
公開日期:	2004
官方說明文件#:	NSC93-2215-E009-011
URI:	http://hdl.handle.net/11536/91373 https://www.grb.gov.tw/search/planDetail?id=1026636&docId=195162
Appears in Collections:	Research Plans

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