針對晶片系統連接網路之驗證與自動合成之研究(II)

Full metadata record

DC Field	Value	Language
dc.contributor.author	周景揚	en_US
dc.contributor.author	JOU JING-YANG	en_US
dc.date.accessioned	2014-12-13T10:32:53Z	-
dc.date.available	2014-12-13T10:32:53Z	-
dc.date.issued	2003	en_US
dc.identifier.govdoc	NSC92-2215-E009-033	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/91769	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=873468&docId=167334	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	針對晶片系統連接網路之驗證與自動合成之研究(II)	zh_TW
dc.title	The Study on Interconnection Verification and Synthesis for SoC (II)	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
Appears in Collections:	Research Plans

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