Full metadata record
DC FieldValueLanguage
dc.contributor.author周景揚en_US
dc.contributor.authorJOU JING-YANGen_US
dc.date.accessioned2014-12-13T10:32:53Z-
dc.date.available2014-12-13T10:32:53Z-
dc.date.issued2003en_US
dc.identifier.govdocNSC92-2215-E009-033zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/91769-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=873468&docId=167334en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.title針對晶片系統連接網路之驗證與自動合成之研究(II)zh_TW
dc.titleThe Study on Interconnection Verification and Synthesis for SoC (II)en_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系zh_TW
Appears in Collections:Research Plans


Files in This Item:

  1. 922215E009033.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.