高性能混合訊號式介面積體電路---子計畫IV：高性能類比數位介面積體電路(II)

Full metadata record

DC Field	Value	Language
dc.contributor.author	吳介琮	en_US
dc.contributor.author	WU JIEH-TSORNG	en_US
dc.date.accessioned	2014-12-13T10:32:53Z	-
dc.date.available	2014-12-13T10:32:53Z	-
dc.date.issued	2003	en_US
dc.identifier.govdoc	NSC92-2215-E009-034	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/91770	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=873471&docId=167335	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	高性能混合訊號式介面積體電路---子計畫IV：高性能類比數位介面積體電路(II)	zh_TW
dc.title	High-Performance Analog-Digital Interface Integrated Circuits (II)	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
Appears in Collections:	Research Plans

Files in This Item:

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.