標題: | Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique |
作者: | Lin, Horng-Chih Tsai, Tzu-I Chao, Tien-Sheng Jian, Min-Feng Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-三月-2011 |
摘要: | The authors present a simple double patterning technique with I-line stepper to define nanoscale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-100-nm gate length. With this approach, polycrystalline silicon (poly-Si) gate with linewidth down to 80 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography. Moreover, ineffectiveness of end point detection in the second poly-Si gate definition is also addressed. For reliable process control in the second etching step, appropriate mask design is found to be essential. Finally, sub-100-nm MOSFETs with or without halo implemented symmetrically or asymmetrically are fabricated and characterized. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3551527] |
URI: | http://dx.doi.org/10.1116/1.3551527 http://hdl.handle.net/11536/9184 |
ISSN: | 1071-1023 |
DOI: | 10.1116/1.3551527 |
期刊: | JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B |
Volume: | 29 |
Issue: | 2 |
結束頁: | |
顯示於類別: | 期刊論文 |