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dc.contributor.authorChang, David Chih-Weien_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorWu, Chung-Juen_US
dc.contributor.authorLee, Jenq-Kuenen_US
dc.contributor.authorChu, Yuan-Huaen_US
dc.contributor.authorWu, An-Yeuen_US
dc.date.accessioned2014-12-08T15:12:02Z-
dc.date.available2014-12-08T15:12:02Z-
dc.date.issued2011-03-01en_US
dc.identifier.issn1939-8018en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s11265-010-0470-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/9220-
dc.description.abstractIn order to develop a low-power and high-performance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. A VLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dual-core PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).en_US
dc.language.isoen_USen_US
dc.subjectParallel Architecture Coreen_US
dc.subjectPACDSPen_US
dc.subjectVLIW DSPen_US
dc.subjectVLIW compileren_US
dc.subjectDVFSen_US
dc.subjectHeterogeneous multicoreen_US
dc.subjectApplication processoren_US
dc.titleParallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Toolsen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s11265-010-0470-0en_US
dc.identifier.journalJOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGYen_US
dc.citation.volume62en_US
dc.citation.issue3en_US
dc.citation.spage373en_US
dc.citation.epage382en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000288023400009-
dc.citation.woscount5-
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