三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I)

Title:	三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I) The Study of Stacked Memory and Functional Devices for Three-Dimensional Integrated Circuits (3D IC) Applications
Authors:	陳冠能 CHEN KUAN-NENG 國立交通大學電子工程學系及電子研究所
Issue Date:	2013
Gov't Doc #:	NSC102-2221-E009-160
URI:	http://hdl.handle.net/11536/92528 https://www.grb.gov.tw/search/planDetail?id=3092503&docId=416788
Appears in Collections:	Research Plans