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三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I)
三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I)
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Date
2013
Authors
陳冠能
CHEN KUAN-NENG
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https://www.grb.gov.tw/search/planDetail?id=3092503&docId=416788
https://ir.lib.nycu.edu.tw/handle/11536/92528
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