三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I)

Full metadata record

DC Field	Value	Language
dc.contributor.author	陳冠能	en_US
dc.contributor.author	CHEN KUAN-NENG	en_US
dc.date.accessioned	2014-12-13T10:34:06Z	-
dc.date.available	2014-12-13T10:34:06Z	-
dc.date.issued	2013	en_US
dc.identifier.govdoc	NSC102-2221-E009-160	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/92528	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=3092503&docId=416788	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I)	zh_TW
dc.title	The Study of Stacked Memory and Functional Devices for Three-Dimensional Integrated Circuits (3D IC) Applications	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系及電子研究所	zh_TW
Appears in Collections:	Research Plans