Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 林清安 | en_US |
dc.contributor.author | LIN CHING-AN | en_US |
dc.date.accessioned | 2014-12-13T10:34:53Z | - |
dc.date.available | 2014-12-13T10:34:53Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.govdoc | NSC91-2215-E009-069 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/93053 | - |
dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=784488&docId=150794 | en_US |
dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | 電路中間聯結的模式簡化---基於平衡實現的方法(II) | zh_TW |
dc.title | Circuit Interconnect Model Reduction---A Balanced Realization Based Approach (II) | en_US |
dc.type | Plan | en_US |
dc.contributor.department | 交通大學電機與控制工程系 | zh_TW |
Appears in Collections: | Research Plans |
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