電極/鐵電薄膜/結緣層/半導體結構之製程與電特性劣化研究(II)

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DC Field	Value	Language
dc.contributor.author	陳三元	en_US
dc.contributor.author	CHEN SAN-YUAN	en_US
dc.date.accessioned	2014-12-13T10:34:54Z	-
dc.date.available	2014-12-13T10:34:54Z	-
dc.date.issued	2002	en_US
dc.identifier.govdoc	NSC91-2215-E009-051	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/93066	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=784427&docId=150777	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	電極/鐵電薄膜/結緣層/半導體結構之製程與電特性劣化研究(II)	zh_TW
dc.title	Processing and Characteristic Degradation of Metal-Ferroelectric-Insulator-Semiconductor (II)	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學材料科學與工程系	zh_TW
Appears in Collections:	Research Plans

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