具有信號處理能力的嵌入式微處理機的實現及應用---子計劃一：嵌入式微處理機微架構設計與驗證及其模擬軟體

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DC Field	Value	Language
dc.contributor.author	吳全臨	en_US
dc.date.accessioned	2014-12-13T10:35:38Z	-
dc.date.available	2014-12-13T10:35:38Z	-
dc.date.issued	2000	en_US
dc.identifier.govdoc	NSC89-2218-E009-057	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/93530	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=597277&docId=112552	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	具有信號處理能力的嵌入式微處理機的實現及應用---子計劃一：嵌入式微處理機微架構設計與驗證及其模擬軟體	zh_TW
dc.title	Microarchitecture Design & Verification of Embedded Microprocessor and its Simulator/Emulator	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學資訊工程學系	zh_TW
Appears in Collections:	Research Plans

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