應用良率分析於生產不同積體電路產品之生產線製造績效評估之研究

Full metadata record

DC Field	Value	Language
dc.contributor.author	唐麗英	en_US
dc.contributor.author	TONG LEE-ING	en_US
dc.date.accessioned	2014-12-13T10:37:31Z	-
dc.date.available	2014-12-13T10:37:31Z	-
dc.date.issued	1999	en_US
dc.identifier.govdoc	NSC88-2213-E009-033	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/94708	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=460934&docId=84442	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	積體電路	zh_TW
dc.subject	良率分析	zh_TW
dc.subject	績效評估	zh_TW
dc.subject	修正卜松模式	zh_TW
dc.subject	Integrated circuit (IC)	en_US
dc.subject	Yield analysis	en_US
dc.subject	Performance evaluation	en_US
dc.subject	Modified Poisson model	en_US
dc.title	應用良率分析於生產不同積體電路產品之生產線製造績效評估之研究	zh_TW
dc.title	Application of Yield Analysis on Manufacturing Performance Evaluation of Integrated Circuits Production Lines	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學工業工程與管理系	zh_TW
Appears in Collections:	Research Plans

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