對稱陣列型現場可程式化閘陣列導線段結構的設計與分析

Full metadata record

DC Field	Value	Language
dc.contributor.author	張耀文	en_US
dc.contributor.author	YAO-WENCHANG	en_US
dc.date.accessioned	2014-12-13T10:37:57Z	-
dc.date.available	2014-12-13T10:37:57Z	-
dc.date.issued	1998	en_US
dc.identifier.govdoc	NSC87-2215-E009-041	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/94967	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=398408&docId=70294	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	場可程式閘列	zh_TW
dc.subject	邏輯模組	zh_TW
dc.subject	導線段	zh_TW
dc.subject	可程式化開關	zh_TW
dc.subject	繞線	zh_TW
dc.subject	可繞度	zh_TW
dc.subject	電腦輔助設計	zh_TW
dc.subject	FPGA	en_US
dc.subject	Logic module	en_US
dc.subject	Wire segment	en_US
dc.subject	Programmable switch	en_US
dc.subject	Routing	en_US
dc.subject	Routability	en_US
dc.subject	Computer-aided design	en_US
dc.subject	CAD	en_US
dc.title	對稱陣列型現場可程式化閘陣列導線段結構的設計與分析	zh_TW
dc.title	Design and Analysis of Symmetric Array-Based FPGA Segmentations	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學資訊科學系	zh_TW
Appears in Collections:	Research Plans

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