積體電路生產線上考慮缺陷群聚現象之修正良率模式

Title:	積體電路生產線上考慮缺陷群聚現象之修正良率模式 Modified Integrated Circuit Yield Model Using Neural Network
Authors:	唐麗英 TONG LEE-ING 交通大學工業工程與管理系
Keywords:	積體電路;良率模式;缺陷群聚;統計分析;類神經網路;Integrated circuit;Yield model;Defect cluster;Statistical analysis;Neural network
Issue Date:	1998
Gov't Doc #:	NSC87-2213-E009-080
URI:	http://hdl.handle.net/11536/95113 https://www.grb.gov.tw/search/planDetail?id=354939&docId=63469
Appears in Collections:	Research Plans