A novel poly-Si nanowire TFT for nonvolatile memory applications

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Hsu, Hsin-Hwei	en_US
dc.contributor.author	Lin, Horng-Chih	en_US
dc.contributor.author	Huang, Jian-Fu	en_US
dc.contributor.author	Huang, Tiao-Yuan	en_US
dc.date.accessioned	2014-12-08T15:02:15Z	-
dc.date.available	2014-12-08T15:02:15Z	-
dc.date.issued	2008	en_US
dc.identifier.isbn	978-1-4244-1656-1	en_US
dc.identifier.uri	http://hdl.handle.net/11536/952	-
dc.description.abstract	A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.	en_US
dc.language.iso	en_US	en_US
dc.title	A novel poly-Si nanowire TFT for nonvolatile memory applications	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	MTTD 2007 TAIPEI: PROCEEDINGS OF 2007 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING (MTD '07)	en_US
dc.citation.spage	55	en_US
dc.citation.epage	56	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000257508500011	-
顯示於類別：	會議論文