積體電路生產線上利用類神經網路方法分析缺陷群聚現象之修正缺陷數管制圖

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	唐麗英	en_US
dc.contributor.author	TONG LEE-ING	en_US
dc.date.accessioned	2014-12-13T10:38:27Z	-
dc.date.available	2014-12-13T10:38:27Z	-
dc.date.issued	1997	en_US
dc.identifier.govdoc	NSC86-2213-E009-035	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/95390	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=269137&docId=47931	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	積體電路	zh_TW
dc.subject	良率	zh_TW
dc.subject	缺陷	zh_TW
dc.subject	波瓦松分配	zh_TW
dc.subject	缺陷數管制圖	zh_TW
dc.subject	類神經網路	zh_TW
dc.subject	群聚	zh_TW
dc.subject	Integrated circuit	en_US
dc.subject	Yield	en_US
dc.subject	Defect	en_US
dc.subject	Poisson distribution	en_US
dc.subject	C-Chart	en_US
dc.subject	Neural network	en_US
dc.subject	Clustering	en_US
dc.title	積體電路生產線上利用類神經網路方法分析缺陷群聚現象之修正缺陷數管制圖	zh_TW
dc.title	Modified Process Control Chart in Integrated Circuits Fabrication---Using Neural Network	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學工業工程與管理系	zh_TW
顯示於類別：	研究計畫