完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | 陳正 | en_US |
| dc.contributor.author | CHEN CHENG | en_US |
| dc.date.accessioned | 2014-12-13T10:38:36Z | - |
| dc.date.available | 2014-12-13T10:38:36Z | - |
| dc.date.issued | 1997 | en_US |
| dc.identifier.govdoc | NSC86-2213-E009-091 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/95533 | - |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=272763&docId=48709 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.subject | 模擬評估環境 | zh_TW |
| dc.subject | 系統架構 | zh_TW |
| dc.subject | 平行編譯 | zh_TW |
| dc.subject | 平行作業系統 | zh_TW |
| dc.subject | 輸出入子系統 | zh_TW |
| dc.subject | 內接網路 | zh_TW |
| dc.subject | 多處理機 | zh_TW |
| dc.subject | 多重匯流排 | zh_TW |
| dc.subject | Simulation and evaluation environment | en_US |
| dc.subject | System architecture | en_US |
| dc.subject | Parallel compilation | en_US |
| dc.subject | Parallel operating system | en_US |
| dc.subject | I/O subsystem | en_US |
| dc.subject | Interconnection network | en_US |
| dc.subject | Multiprocessor | en_US |
| dc.subject | Hyberbus | en_US |
| dc.title | 可延伸多處理機系統架構設計之研究－總計畫(II) | zh_TW |
| dc.title | Study of System Architecture Design for Scalable Mulitprocessors(II) | en_US |
| dc.type | Plan | en_US |
| dc.contributor.department | 交通大學資訊工程研究所 | zh_TW |
| 顯示於類別： | 研究計畫 | |
