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dc.contributor.author張隆國en_US
dc.date.accessioned2014-12-13T10:38:37Z-
dc.date.available2014-12-13T10:38:37Z-
dc.date.issued1997en_US
dc.identifier.govdocNSC86-2221-E009-063zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/95536-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=271930&docId=48506en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.subject構裝zh_TW
dc.subject電導係數zh_TW
dc.subject熱傳導率zh_TW
dc.subject多晶片模組zh_TW
dc.subjectPackagingen_US
dc.subjectElectrical conductivityen_US
dc.subjectThermal conductivityen_US
dc.subjectMCMen_US
dc.subjectSPICEen_US
dc.title高密度電子構裝接合與測試載具之開發---以SPICE對積體電路與構裝基板之高效率熱模擬與電性分析(I)zh_TW
dc.titleEfficient Thermal Model of IC's and Packaging Substrate and Their Model in SPICE(I)en_US
dc.typePlanen_US
dc.contributor.department交通大學電機與控制工程研究所zh_TW
顯示於類別:研究計畫