高密度電子構裝接合與測試載具之開發---以SPICE對積體電路與構裝基板之高效率熱模擬與電性分析(I)

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	張隆國	en_US
dc.date.accessioned	2014-12-13T10:38:37Z	-
dc.date.available	2014-12-13T10:38:37Z	-
dc.date.issued	1997	en_US
dc.identifier.govdoc	NSC86-2221-E009-063	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/95536	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=271930&docId=48506	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	構裝	zh_TW
dc.subject	電導係數	zh_TW
dc.subject	熱傳導率	zh_TW
dc.subject	多晶片模組	zh_TW
dc.subject	Packaging	en_US
dc.subject	Electrical conductivity	en_US
dc.subject	Thermal conductivity	en_US
dc.subject	MCM	en_US
dc.subject	SPICE	en_US
dc.title	高密度電子構裝接合與測試載具之開發---以SPICE對積體電路與構裝基板之高效率熱模擬與電性分析(I)	zh_TW
dc.title	Efficient Thermal Model of IC's and Packaging Substrate and Their Model in SPICE(I)	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電機與控制工程研究所	zh_TW
顯示於類別：	研究計畫