單晶片多處理機設計之研究---子計畫IV：單晶片多處理機可程式實驗平台之設計與實現

Full metadata record

DC Field	Value	Language
dc.contributor.author	王國禎	en_US
dc.date.accessioned	2014-12-13T10:38:43Z	-
dc.date.available	2014-12-13T10:38:43Z	-
dc.date.issued	1997	en_US
dc.identifier.govdoc	NSC86-2213-E009-085	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/95600	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=279552&docId=50373	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	單邊縱橫交換鍵	zh_TW
dc.subject	容錯	zh_TW
dc.subject	標準硬體描述語言	zh_TW
dc.subject	場可程式閘陣列	zh_TW
dc.subject	對稱式多處理機晶片	zh_TW
dc.subject	可程式電路板	zh_TW
dc.subject	One-sided crossbar switch	en_US
dc.subject	Fault tolerance	en_US
dc.subject	VHDL	en_US
dc.subject	FPGA	en_US
dc.subject	Symmetric multiprocessor	en_US
dc.subject	Programmable circuit board	en_US
dc.title	單晶片多處理機設計之研究---子計畫IV：單晶片多處理機可程式實驗平台之設計與實現	zh_TW
dc.title	Design and Implementation of a Programmable Experimental Platform for a Single Chip with Multiple CPUs	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學資訊科學系	zh_TW
Appears in Collections:	Research Plans