超大型積體電路之測試與可測試性設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	李崇仁	en_US
dc.date.accessioned	2014-12-13T10:39:10Z	-
dc.date.available	2014-12-13T10:39:10Z	-
dc.date.issued	1996	en_US
dc.identifier.govdoc	NSC85-2215-E009-026	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/96160	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=231477&docId=42172	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	超大型積體電路	zh_TW
dc.subject	可測試性	zh_TW
dc.subject	延遲障礙	zh_TW
dc.subject	障礙模擬	zh_TW
dc.subject	網路測試	zh_TW
dc.subject	VLSI	en_US
dc.subject	Testability	en_US
dc.subject	Delay fault	en_US
dc.subject	Fault simulation	en_US
dc.subject	Network testing	en_US
dc.title	超大型積體電路之測試與可測試性設計	zh_TW
dc.title	Testing and Design for Testability for General VLSI	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系	zh_TW
Appears in Collections:	Research Plans