超大型積體電路之測試與可測試性設計

Title:	超大型積體電路之測試與可測試性設計 Testing and Design for Testability for General VLSI
Authors:	李崇仁國立交通大學電子工程學系
Keywords:	超大型積體電路;可測試性;延遲障礙;障礙模擬;網路測試;VLSI;Testability;Delay fault;Fault simulation;Network testing
Issue Date:	1996
Gov't Doc #:	NSC85-2215-E009-026
URI:	http://hdl.handle.net/11536/96160 https://www.grb.gov.tw/search/planDetail?id=231477&docId=42172
Appears in Collections:	Research Plans