Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 周景揚 | en_US |
dc.contributor.author | JOU JING-YANG | en_US |
dc.date.accessioned | 2014-12-13T10:39:15Z | - |
dc.date.available | 2014-12-13T10:39:15Z | - |
dc.date.issued | 1995 | en_US |
dc.identifier.govdoc | NSC84-2514-S009-003 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/96249 | - |
dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=226400&docId=40714 | en_US |
dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 超大型積體電路設計 | zh_TW |
dc.subject | 超大型積體電路測試 | zh_TW |
dc.subject | 可測試性設計 | zh_TW |
dc.subject | VLSI design | en_US |
dc.subject | VLSI testing | en_US |
dc.subject | Design for testability | en_US |
dc.title | 超大型積體電路測試與可測性設計課程發展---子計畫(I):總論、組合測試、序向測試、設計通例 | zh_TW |
dc.title | "VLSI Testing and Design for Testability" Course Development Fundamentals and Design Methodology, Combinational Circuit Testing ,Sequential Circuit Testing and Design Examples | en_US |
dc.type | Plan | en_US |
dc.contributor.department | 國立交通大學電子工程學系 | zh_TW |
Appears in Collections: | Research Plans |