BiCMOS低電壓積體電路設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	吳介琮	en_US
dc.contributor.author	WU JIEH-TSORNG	en_US
dc.date.accessioned	2014-12-13T10:39:42Z	-
dc.date.available	2014-12-13T10:39:42Z	-
dc.date.issued	1995	en_US
dc.identifier.govdoc	NSC84-2622-E009-008	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/96754	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=150264&docId=24762	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	BiCMOS低電壓積體電路設計	zh_TW
dc.title	Bicmos Low-Voltage Integrated Circuit Design	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程研究所	zh_TW
Appears in Collections:	Research Plans