| Title: | 超大型積體電路設計與計算機自動輔助設計---子計畫三：多階邏輯之功率估測與低面積低功率電路合成系 The Study of Power Estimation and Multilevel Logic Synthesis for Area/Power Reduction |
| Authors: | 沈文仁 國立交通大學電子工程學系 |
| Issue Date: | 1995 |
| Gov't Doc #: | NSC84-2215-E009-059 |
| URI: | http://hdl.handle.net/11536/96848 https://www.grb.gov.tw/search/planDetail?id=160992&docId=26779 |
| Appears in Collections: | Research Plans |
