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dc.contributor.authorChang, Wei-Jenen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorLai, Tai-Xiangen_US
dc.contributor.authorTang, Tien-Haoen_US
dc.contributor.authorSu, Kuan-Chengen_US
dc.date.accessioned2014-12-08T15:12:36Z-
dc.date.available2014-12-08T15:12:36Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1014-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/9690-
dc.description.abstractThe ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated, that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.en_US
dc.language.isoen_USen_US
dc.titleThe impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS processen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITSen_US
dc.citation.spage249en_US
dc.citation.epage252en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000251130700047-
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