完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Wei-Jen | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.contributor.author | Lai, Tai-Xiang | en_US |
dc.contributor.author | Tang, Tien-Hao | en_US |
dc.contributor.author | Su, Kuan-Cheng | en_US |
dc.date.accessioned | 2014-12-08T15:12:36Z | - |
dc.date.available | 2014-12-08T15:12:36Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-1014-9 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/9690 | - |
dc.description.abstract | The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated, that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | IPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | en_US |
dc.citation.spage | 249 | en_US |
dc.citation.epage | 252 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000251130700047 | - |
顯示於類別: | 會議論文 |