標題: ESC robustness of 40-V CMOS devices with/without drift implant
作者: Chang, Wei-Jen
Ker, Ming-Dou
Lai, Tai-Hsiang
Tang, Tien-Hao
Su, Kuan-Cheng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.
URI: http://hdl.handle.net/11536/17476
http://dx.doi.org/10.1109/IRWS.2006.305237
ISBN: 978-1-4244-0296-0
ISSN: 1930-8841
DOI: 10.1109/IRWS.2006.305237
期刊: 2006 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT
起始頁: 167
結束頁: 170
顯示於類別:會議論文


文件中的檔案:

  1. 000245236100039.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。