标题: | BIST for measuring clock jitter of charge-pump phase-locked loops |
作者: | Hsu, Jen-Chien Su, Chauchin 电控工程研究所 Institute of Electrical and Control Engineering |
关键字: | analog built-in self-test (BIST);jitter measurement;on-chip measurement;phase-locked loop (PLL) BIST;time-to-digital converter (TDC) |
公开日期: | 1-二月-2008 |
摘要: | This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%. |
URI: | http://dx.doi.org/10.1109/TIM.2007.910109 http://hdl.handle.net/11536/9691 |
ISSN: | 0018-9456 |
DOI: | 10.1109/TIM.2007.910109 |
期刊: | IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT |
Volume: | 57 |
Issue: | 2 |
起始页: | 276 |
结束页: | 285 |
显示于类别: | Articles |
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