Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors

Abstract

A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.