多晶片模組設計自動化與測試系統---子計畫四：多晶片模組可測性設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	郭斯彥	en_US
dc.contributor.author	KUO SY-YEN	en_US
dc.date.accessioned	2014-12-13T10:40:11Z	-
dc.date.available	2014-12-13T10:40:11Z	-
dc.date.issued	1994	en_US
dc.identifier.govdoc	NSC83-0404-E002-058	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/97246	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=109856&docId=17488	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	多晶片模組設計自動化與測試系統---子計畫四：多晶片模組可測性設計	zh_TW
dc.title	Design for Testability and Diagnosis in Multichip Modules	en_US
dc.type	Plan	en_US
dc.contributor.department	國立台灣大學電機工程學研究所	zh_TW
Appears in Collections:	Research Plans