前瞻性混合信號式電路設計技術開發-子計畫三：高性能類比數位轉換技術(II)

Abstract

本計畫將研究在奈米CMOS 製程下設計高性能的類比數位轉換器（ADC）。雖然是混合 訊號式積體電路設計，但我們將強調利用數位信號處理（DSP）的技術來彌補先進製程所造 成的非理想效應，進而提升整體系統功能或簡化類比電路。簡化後的類比電路將比較容易設 計，可隨著技術演化，而且容易在短時間中移植至不同廠商的製程中。 本計畫規劃的研究方向如下：（1）高速Switched-Capacitor Delta-Sigma Modulator；（2） 高速Continuous-Time Delta-Sigma Modulator；（3）超高速Time-Interleaved ADC。 我們將設計一個20MHz 訊號頻寬85dB SNDR 的離散時間式Switched-Capacitor Delta-Sigma Modulator。我們將簡化運算放大器電路，並用數位校正技術來提升解析度以及降 低功率消耗。我們將設計一個20MHz 訊號頻寬85dB SNDR 的Continuous-Time Delta-Sigma Modulator。我們會開發新式電路來補償時脈抖動造成的誤差。我們將設計一個取樣率為100 GS/s 解析度至少4-Bit 的超高速Time-Interleaved ADC。我們將使用多路Flash ADC，並開發 新式的校正技術來修正A/D 渠道不匹配的問題。 本計畫所設計的電路皆會以 45 nm 或更先進的 CMOS 製作成晶片並加以量測，以驗證 所發展的技術的可行性。所發展的晶片都會以「晶片效能指標」（Chip Performance Index, CPI） 來和功能類似的晶片相比較。而本計畫的目標就是追求最佳的 CPI。

This project is to design analog-to-digital converters (ADC) in nanoscale CMOS technologies. Although they are mixed-signal designs, we will emphasize the use of digital signal processing to compensate the unfavorable effects on analog circuitry caused by advanced technologies. The objectives are to improve overall all system performance and/or simplify analog circuitry. Simpler analog circuits are easier to design, can scale along with technologies, and take less man-hour to do technology migration. This project is focused on (1) high-speed switched-capacitor Delta-Sigma modulator (DSM); (2) high-speed continuous-time DSM; and (3) ultra-high-speed time-interleaved ADC. We will design a discrete-time switched-capacitor DSM with 20 MHz signal bandwidth and 85 dB SNDR. We will simplify operational amplifiers, and use digital calibration to improve ADC resolution and reduce power dissipation. We will design a continuous-time DSM with 20 MHz signal bandwidth and 85 dB SNDR. We will develop new circuit to compensate errors caused by clock jitter. We will design a 100-GS/s ultra-high-speed time-interleaved ADC with a resolution of at least 4 bits. We will use flash ADCs for A/D channels. We will develop new calibration techniques to correct the errors caused by inter-channel mismatches. All circuits designed in this project will be fabricated using 45nm or more advanced CMOS technologies. The chips will be characterized to validate the design techniques developed in this project. We will compare the chips with similar designs against the chip performance index (CPI). Our objective is to achieve the best CPI.