奈米CMOS模型研發以探討應力工程與佈局效應對於高頻特性與寬頻雜訊之影響(I)

Abstract

隨著 CMOS 技術之神速發展進入奈米領域，其中由材料與製程產生的應力，無論 是天然內在的或者應力工程產生的，均與元件平面佈局和立體結構有密切關聯。STI 製程產生之應力乃是內在的。至於應力工程則包括壓縮型之e-SiGe 加諸於pMOS、伸 張型之CESL 加於nMOS、或者壓縮/伸張型之應力內襯膜分別應用於nMOS/pMOS， 其目的乃是提升mobility。上述各種應力雖來源不同，但是對於佈局之敏感性乃是共通 的。並且所有應力均會對奈米元件之特性產生顯著影響，不限於mobility、電流、gate 速度，乃擴及高頻特性與寬頻雜訊。然而針對此議題，無論是實驗數據或者機制理論 皆呈現諸多衝突與矛盾。根據審慎評估， 其中不一致性可能大多來自量測方法潛在之 問題與先天之限制，此問題對於奈米元件更加嚴重。現有大家熟知常用之電性量測方 法均存在諸多缺陷與限制，例如探針、連線與矽基板等之寄生效應而產生之損耗，包 括低頻時之電阻式損耗與高頻操作時之電容電感耦合效應等。此外，超薄之閘極介電 層因量子穿隧效應產生之漏電流導致傳統之C-V 與CP 量測方法出現重大問題。總合 上述各類問題與缺陷，如何精確地萃取奈米元件之本質參數，如Lg、Leff、Weff、Tox(inv)、 Cox(inv) 與 Qinv，乃成為一極具挑戰性之研究課題。更重要的是，這些元件本質參數乃直 接決定了關鍵性功能參數，如μeff、gm、fT、fmax 以及雜訊如NFmin 與Sid。前述之困難乃 增加了奈米元件模型建立與模擬方面之挑戰，尤其是高頻與低雜訊之設計面臨之難 題。本三年期計畫之第一期乃針對此課題，將建立一創新之奈米元件量測分析方法， 其中包含新的測試結構、高頻S-參數量測與改進之去寄生效應方法，以及三維連線模 擬等等。 ｢動態基極偏壓｣方法已被證實可有效達到低電壓與低功耗。本計畫擬應用此方法 以達到低電壓並提升mobility 與電流之目的。前述之應力工程與此｢動態基極偏壓｣法 均可提升mobility，但是對於雜訊之影響可能大異其趣。其主要差異源自改變mobility 之物理機制不同。應力工程對mobility 之調變是藉著晶格不匹配產生之扭曲與能帶結 構改變，然而｢動態基極偏壓｣乃是受益於較低之等效電場而減少載子表面碰撞以提升 其mobility。因此本計畫擬致力於探討此兩種方法對於mobility、高頻特性與低頻雜訊 之影響，包括flicker noise 與random telegraph noise (RTN)。其中包含四埠測試結構設 計、元件量測分析與參數萃取等等。本計畫之第二期有三個重點主題 (1) 低頻雜訊模 型之改進，加入元件佈局效應(2) BSIM-4 模型之改進，加入佈局效應相關之雜訊模型 以及｢動態基極偏壓｣效應，以期適用於四埠元件模擬(3) 四埠元件之小訊號等效電路 模型建立以應用於使用｢動態基極偏壓｣之高頻電路模擬。 雙閘極 MOSFET 乃是一新式的cascode 結構，實際為單一元件佈局而具有二個獨 立的閘極以提供個別之電壓，其中雙閘極分別控制之二個電晶體乃共有源極與汲極以 減少面積。此結構中之共有源/汲極區域稱為inter-stage 乃處於懸浮態無任何接觸窗與 連線，因此呈現有趣的佈局效應，對於I-V、C-V 與高頻特性均有極大影響，因此列為 本計畫之第三期研究主題。其中主要挑戰包括如何決定源自inter-stage 的閘極電容、接 面電容與串聯電阻，因其乃處於懸浮態而無法直接量測。此雙閘極MOSFET 實際結構 上為5 端元件，因此四埠測試是必要的，但是不足以得到所有的元件參數，預期必需 加入另一四埠測試結構稱為common-gate MOSFET，以期解決此難題。本計畫之第三 期研究擬完成之工作為(1) 雙閘極MOSFET 之小訊號等效電路模型建立以應用於使用 此新式cascode 之高頻電路模擬 (2) BSIM-4 模型之改進，加入雙閘極MOSFET 元件模 型參數，以期適用於新式cascode 模擬(3) 射頻電路設計包括LNA 與 mixer，以比較 新式cascode 與傳統cascode 之差異與優缺點。 總之，本三年期計畫涵蓋之研究主題深具挑戰性，並且兼具學術研究與實用價值。 本計畫擬達成之目標與成果，有助於提升奈米CMOS 射頻與類比電路設計之效能。

With the advancement of CMOS technology into nanoscale regime, the stress introduced from materials and processes, either intrinsically or intentionally becomes critically sensitive to the device layout and topography. STI process introduced strain is well known as the kind of intrinsic stress. e-SiGe for pMOS, tensile CESL for nMOS, or dual stress liner for both nMOS and pMOS, have been developed as strain engineering for mobility enhancement. All of the mentioned stressors, even coming from different sources have a common nature of strong layout dependence and will impose a dramatic impact on CMOS device performance, not only mobility, current, and gate speed, but also on high frequency performance and broadband noise. However, there exist a lot of controversies on this subject, either from experimental results or proposed mechanisms. Most of the contradictions may be originated from the intrinsic problems and limitations of the characterization methods, which become particularly worse on nanoscale devices. Most of the popular methods suffer the parasitic effects from probing, interconnection lines, and lossy substrate, which can be in the form of resistive loss at lower frequency or capacitive and inductive coupling at higher frequency. Gate tunneling leakage appears as a show-stopper to conventional C-V and CP measurement. Altogether, they bring a tough problem to the extraction of intrinsic device parameters, such as Lg, Leff, Weff, Tox(inv), Cox(inv), and Qinv, which are basic parameters to determine μeff, gm, fT, fmax, and noise like NFmin and Sid. The mentioned challenges add difficulty to nanoscale device modeling and simulation, particularly for high frequency and low noise design. In the first phase of this project, a new characterization method incorporating new test structures, high frequency S-parameters measurement and improved deembedding, and 3-D interconnect simulation will be developed to provide a concrete solution to this subject. Dynamic body bias (DBB), which has been proven effective for low voltage and low power design, is proposed as a promising approach to higher mobility and current at lower voltage. Both strain engineering and DBB can realize mobility enhancement but the impact on noise may be quite different. The basic difference comes from the mechanism responsible for mobility modulation. The former one relies on the lattice mismatch and resulted band structure modulation but the latter one benefits from lower Eeff and less surface scattering. It appears as one more interesting subject worthy of investigation. In this project, an extensive effort will be focused on DBB and strain effect on mobility, high frequency performance, and low frequency noise (LFN) like flicker noise and random telegraph noise (RTN). 4-port test structure design, device characterization, and parameters extraction will be covered for this work, based on the foundation established in the first phase. The major research effort in the second phase can be focused on 3 subjects, such as LFN model enhancement and consolidation for layout dependent effect, BSIM-4 model enhancement for 4T MOSFET with layout dependent stress and DBB effect, and a small signal equivalent circuit model for 4-port MOSFET with mentioned features. Dual-gate MOSFET proposed as a new cascode for smaller chip area incorporates interesting layout dependent effects on I-V, C-V, and high frequency performance and is selected as the core subject in the third phase of this project. The major challenge comes from the determination of inter-stage gate capacitances, inter-stage junction capacitances, and inter-stage sheet resistance, all associated with the merged S/D region, which is floated without any contacts. 4-port S-parameters measurement is indispensable but not sufficient for a dual-gate MOSFET actually with 5 electrodes. Common-gate MOSFET is proposed as one more test structure working with dual-gate MOSFETs as a potential solution to this problem. In this approach, a small signal equivalent circuit model can be established for this new cascode simulation and applied to RF circuits design. Also, the critical model parameters associated with the floating node can be deployed in BSIM-4 to enable simulation for dual-gate MOSFET. Finally, LNA and mixer will be designed and fabricated for a benchmark on the conventional and new cascades. In summary, all of the subjects specified in this 3-year project are challenging and deserve extensive research effort. The achievements to be realized by this project can facilitate RF and analog circuits design using nanoscale CMOS technology.