面板低溫記憶體元件技術開發

Abstract

在本專題計畫中，我們提出數種自行構思與發展的新穎且與面板製程相容之記憶體元件，包含各式非揮發性記憶體及動態/靜態隨機存取記憶體元件，且使用低溫電漿輔助化學氣相與原子層沉積系統取代以往的高溫低壓化學氣相沉積系統，使製程低溫化以符合面板之製程要求。非揮發性記憶體中，著重於SONOS之結構，發展單閘/雙閘平面式及多閘極奈米線記憶體之低溫製程技術。並透過調整電荷捕捉層(如調整氮化矽元素組成比或是更換成高介電常數材料)，增加感測窗口與改善元件的特性。在動態隨機存取記憶體方面，我們捨棄傳統1T/1C之標準結構，研究一新穎操作模式之單電晶體之動態隨機存取記憶體；藉由製程的改良也能完成奈米線反相器與靜態隨機存取記憶體。本研究計畫所提出與開發之新穎奈米線電子記憶體元件結構與製造技術，相信在可量產和再現性高之訴求下，可達成低耗能、低電壓操控、高性能、及高可靠度之要求，並進一步評估應用於面板嵌入式記憶體技術之未來發展。

In this project, we propose and intend to develop several novel memory devices compatible with flat-panel processing, including nonvolatile memory, DRAM, and SRAM devices. To fabricate the devices, low-temperature deposition tools like plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) will be employed for forming the dielectric layers in order to meet the low process temperature requirement in the manufacturing of flat-panel products. For the nonvolatile memory, we focus on the SONOS-type memory and will develop the single and double-gated planar as well as and multi-gated nanowire memory devices. Efforts will be done to enlarge the sensing window by charge trapping layer engineering (for example, by tuning the element composition ratio of SiNx or using high dielectric constant materials) and to improve in device performance by adopting novel device structure such as the nanowire channel. We will also study the operating mechanism of a novel device with a suspended nanowire channel and explore it capability for DRAM application. Furthermore, with a slight process modification, a NW-based inverter and the associated SRAM cell are proposed and will be fabricated and studied.