開發具量產優勢高性能奈米點狀摻雜底閘極a-IGZO TFT及其物理分析

Abstract

本計畫欲在兩年期內開發出具量產能力的高效能、高穩定度的奈米點摻雜之底閘極銦鎵鋅氧化物薄膜電晶體，目標效能在操作電壓10伏內達到載子遷移率 80 cm2/Vs，其元件穩定度在閘極與臨界偏壓差正負20伏連續偏壓 3600 秒內的臨界電壓位移小於 2 伏特。本計畫提出的奈米點狀摻雜概念為本實驗室之創新想法，先期成果已經成功在頂閘極自我對準之非晶銦鎵鋅氧化物薄膜電晶體得到約80 cm2/Vs的高載子遷移率，相關成果發表於高影響力期刊Advanced Materials中。本計劃將解決先期成果量產性的兩大問題點：與現行量產技術之相容性以及元件的可靠度，希望使奈米點攙雜可以成功應用到量產技術中。第一年，奈米孔洞結構仍先承襲本實驗室以往的自組裝奈米球製程，但改使用底閘極結構開發製程，將嘗試利用氬氣電漿處理、紫外光照射、電漿輔助式化學氣相沉積的氫摻雜方式，以及原子層沉積一層超薄氧化鋁覆蓋層當作摻雜層等不同方式，做載子摻雜於奈米點狀結構的技術。此外，我們將利用共濺鍍技術去調控薄膜內銦、鎵、鋅的比例組成，製作最佳化奈米點狀摻雜之銦鎵鋅氧化物薄膜電晶體。同時我們將利用模擬軟體；Silvaco TCAD，及高解析電子能譜儀等其他輔助分析設備，探討奈米點狀摻雜效能與不同銦、鎵、鋅成分之元件的影響及其物理機制，預計達到計畫目標之一：操作電壓10伏內達到載子遷移率 80 cm2/Vs。第二年，預計開發具量產能力的高度規則孔洞化技術，包含奈米壓印以及緊密堆積奈米球搭配電漿蝕刻技術等方式，來替代目前不規則分布的奈米球製程，同時將開發保護層製程來提升元件的穩定度達閘極與臨界偏壓差正負20伏連續偏壓 3600 秒內的臨界電壓位移小於 2 伏特。

The aim of this two-years proposal is to develop high-performance and stable amorphous In-Ga-Zn oxide (a-IGZO) bottom-gate thin film transistor (TFT) by nano-dot doping (NDD) technique. The NDD technique is a new concept proposed by our lab in 2011. With nanometer dot-like doping in channel region, we successfully increase the effective electron mobility in top-gate a-IGZO TFT to be around 80 cm2/Vs. The work was published in high-impact journal, Advanced Materials. In this project, we want to solve two major issues in our NDD a-IGZO TFT. The two issues are the process compatibility and the stability. Our targets in this project are as follows. 1. Devices with high mobility- 80 cm2/Vs under operative voltage 10 V, 2. Devices with high stability- threshold voltage shift lower than 2 V under VG-VTH bias stress ±20 V in 3600 second. In the first year, we will use several techniques such as Ar plasma, UV light irradiation, H+ doping by PECVD and deposition ultra thin film Al2O3 by ALD, as the carrier doping in IGZO film in bottom-gate a-IGZO TFT. The nanometer dot-like structure will be made by polystyrene (PS) balls process which is already well developed in our lab. We will also adjust the In, Ga and Zn component of IGZO film by co-sputter to optimize the NDD a-IGZO TFT. In the meantime, we use Silvaco TCAD and XPS to analyze and discuss the mechanism of NDD effect. In this step, we expect to fabricate the high mobility bottom-gate NDD a-IGZO TFT with 80 cm2/Vs under operative voltage 10 V. In the second year, we try to build the producible highly regular arrangement porous nano structure by close-packed PS balls or nano-inprint techniques. We will also develop the passivation process on NDD a-IGZO TFT to improve device stability. The targeted threshold voltage shift under VG-VTH bias stress ±20 V in 3600 second should be smaller than 2 V.