應用於三維邏輯電路與非揮發性記憶體之先進奈米線技術

Abstract

在本專題計畫中，我們提出數種自行構思與發展的新穎奈米線元件結構，包括有：獨立雙閘，環繞閘與懸浮式奈米線元件，並開發相關的製程技術。雙閘與環繞閘結構的開發主要目標在於探索非揮發記憶體在低電壓下進行高效率的寫入/抹除動作，並具有良好的資料保存時間，藉由製程的改良也能完成奈米線反相器與環狀震盪器，而懸浮奈米線閘極元件更是只需兩次微影步驟便能製作出具垂直通道的電晶體。同時在此計畫中將進行具有高載子遷移率之鍺奈米線的開發和分析，並可與矽奈米線整合成高性能之互補式金氧半電晶體元件。由於多晶矽或鍺的低溫化製程特色，上述的元件結構可以三維堆疊的方式整合於高性能之互補式金氧半電晶體元件電路上，完成所謂的三維整合晶片。本研究計畫所提出與開發之新穎奈米線電子元件結構與製造技術，相信在可量產和再現性高之訴求下，可達成高記憶容量、低電壓操控、高性能、及高可靠度之要求，並進一步應用於相關領域和產品，以因應多元化奈米電子應用紀元的來臨。

In this project we propose several new nanowire (NW) device structures, including independent double-gate (IDG), gate-all-around (GAA) and suspended NW devices, and intend to develop the associated device fabrication technology. The IDG and GAA devices are designed and fabricated to explore the feasibility of achieving high programming/erasing efficiency with low operational voltage and to enhance retention characteristics. With a slight process modification, NW-based inverter and ring oscillator are fabricated as well. Besides, there are only two photolithographic steps required to accomplish a NW-sized suspended-gate device with vertical channels. High-mobility Ge NW FETs are also developed, which when integrated with Si counterparts are expected to achieve high performance CMOS devices. Owing to the low temperature processing capability of polycrystalline layers, it is feasible to fabricate aforementioned devices stacked over the bulk CMOS circuits. Such 3D integration allows the increase in the functionality of a chip. Accounting for the high manufacturability and reproducibility of processing technique as well as the new device concepts introduced in the project, the device technologies developed in the work should be available for manufacturing of advanced chips and related products.