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dc.contributor.authorLi, Yimingen_US
dc.contributor.authorHuang, Jung Y.en_US
dc.contributor.authorLee, Bo-Shianen_US
dc.date.accessioned2014-12-08T15:12:49Z-
dc.date.available2014-12-08T15:12:49Z-
dc.date.issued2008-01-01en_US
dc.identifier.issn0268-1242en_US
dc.identifier.urihttp://dx.doi.org/10.1088/0268-1242/23/1/015019en_US
dc.identifier.urihttp://hdl.handle.net/11536/9871-
dc.description.abstractIn this paper, single-grain-boundary(GB)-position-induced electrical characteristic variations in 300 nm surrounding- gate (i.e., gate-all-around (GAA)) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of a single GB near the drain side has an bad effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of the threshold voltage can be reduced from 15% to 5%, with varying gate structures of the GAA polysilicon TFT.en_US
dc.language.isoen_USen_US
dc.titleEffect of the single grain boundary position on surrounding-gate polysilicon thin film transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1088/0268-1242/23/1/015019en_US
dc.identifier.journalSEMICONDUCTOR SCIENCE AND TECHNOLOGYen_US
dc.citation.volume23en_US
dc.citation.issue1en_US
dc.citation.epageen_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.department光電工程學系zh_TW
dc.contributor.department顯示科技研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.contributor.departmentDepartment of Photonicsen_US
dc.contributor.departmentInstitute of Displayen_US
dc.identifier.wosnumberWOS:000253279700019-
dc.citation.woscount12-
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