Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tsai, Tzu-I | en_US |
dc.contributor.author | Lin, Horng-Chih | en_US |
dc.contributor.author | Jian, Min-Feng | en_US |
dc.contributor.author | Huang, Tiao-Yuan | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.date.accessioned | 2014-12-08T15:12:51Z | - |
dc.date.available | 2014-12-08T15:12:51Z | - |
dc.date.issued | 2010-05-01 | en_US |
dc.identifier.issn | 0026-2714 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.microrel.2010.01.019 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/9899 | - |
dc.description.abstract | We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal-oxide-semiconductor field-effect transistors. Excellent device characteristics were verified. (C) 2010 Elsevier Ltd. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A simple method for sub-100 nm pattern generation with I-line double-patterning technique | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.doi | 10.1016/j.microrel.2010.01.019 | en_US |
dc.identifier.journal | MICROELECTRONICS RELIABILITY | en_US |
dc.citation.volume | 50 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | 584 | en_US |
dc.citation.epage | 588 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000278728700002 | - |
Appears in Collections: | Conferences Paper |
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