GreenArmy：綠色微雲伺服系統晶片平台技術-子計畫五：綠色微雲伺服系統晶片上適應性網路與虛擬化加速器之硬體設計( I )

Abstract

本計畫的研究重點在於發展Cloudlet Server On Chip中晶片網路上資料傳輸的關鍵硬體技術與虛擬機器（Virtual Machine）管理硬體模組。總計畫中所提出的Cloudlet Server On Chip系統架構是由多顆處理器區塊 (Processor Tile) 所組成。整體的系統架構支援多個虛擬化機器(VM)同時運作，而每個虛擬機器會由不同的處理器群集(Processor Clusters)來負責執行。隨著半導體技術和系統整合技術的快速成長，未來的Cloudlet Server On Chip預計會包含數十甚至數百顆處理器區塊。在用有如此大量的系統資源的情況下，如何能有效的使用這些資源，成為影響Cloudlet Server On Chip系統效能的重要研究議題。為了有效的支援不同的虛擬機器的運算需求，以及支援不同執行緒之間的特性，Cloudlet Server 必須要能夠調整並重組運算資源的分配。可重組化的晶內網路可以調整並支援合適的系統資源分配。然而，本計畫的實驗結果顯示，平行應用的執行特性必須要同時被考量，才能充分展現晶內網路的可重組化特性的好處。晶內網路必須要根據平行應用的特性，調整網路的聯線方式和傳輸機制。因此，本計畫第一年的研究方向著重在以下兩點：（1）評估並最佳化多執行緒程式中的資料共享特性（2）評估並發展可重組化的晶內網路本計畫所提出的相似性（affinity-based）最佳化方法，在多核心系統中可以減少56.7%的快取記憶體存取，並進而減少52.8%的快取記憶體的存取失敗。而所提出的兩階層混合式晶內網路架構，也能在區域性資料傳輸比例較高時，比完全以mesh建構的網路架構擁有較佳的傳輸延遲。

The main goal of this project is to design the adaptive on-chip interconnection network and virtual machine co-processor for Cloudlet Server On Chip. According to the main proposal, the system architecture of the Cloudlet Server On Chip consists of multiple processor tiles. The Cloudlet system can support multiple active virtual machines (VM‘s) concurrently. Each VM is executed by a dedicated processor cluster, which is composed of multiple processor tiles. Due to the fast pace of the semiconductor scaling and the advances of system integration, the future Cloudlet Chip is expected to contain tens to hundreds of processor tiles. Given such abundant computing resources in a system, how to effectively and efficiently exploit the resources becomes a critical performance issue.In order to effectively support the different requirements of VM‘s as well as the diverse characteristics of multiple threads in a VM, the Cloudlet Server needs to enable the reconfiguration on the computation resources. The reconfigurable on-chip interconnection can facilitate the appropriate distribution of system resources. However, the research results of this project shows that the benefits of the reconfigurable on-chip interconnection can be fully exploited when the characteristics of parallel applications are taken into account. The on-chip network needs to adjust the interconnection property based on the attributes of the applications. Therefore, the focuses of the project in the first year are categorized into two parts. (1) Evaluation and optimization of the data sharing of multi-threaded programs(2) Development and evaluation of the reconfigurable on-chip interconnectionThe proposed affinity-based optimization methodology can achieve up to 56.7% and 52.8% reductions of cache requests and misses on a many-core system. The proposed two-layer hybrid reconfigurable on-chip interconnection has also been proved to have shorter latencies for high locality traffic when compared with a pure mesh network.