標題: | 次世代智慧型加護病房照護系統-子計畫四:應用於次世代智慧型ICU之低功耗多核生醫信號處理系統晶片平台設計( I ) An Energy-Aware Multiprocessor Soc Platform for Biomedical Signal Computing Based on Next Generation Intelligent Intensive Care Unit Health-Care Systems |
作者: | 方偉騏 Fang Wai-Chi 國立交通大學電子工程學系及電子研究所 |
關鍵字: | 加護病房;數位訊號處理;腦波;心電圖;血氧飽和濃度;Intensive Care Unit (ICU);Digital Signal Processing (DSP);Electroencephalography (EEG);Electrocardiography (EKG);Oxygen saturation (SpO2) |
公開日期: | 2011 |
摘要: | 本計畫將提出應用於次世代智慧型ICU 之低功耗多核生醫信號處理系統晶片平台設計,此計畫包含心電訊號處理器、腦訊號處理器、以及生醫影像處理器等關鍵技術。心電訊號處理器包含心律分析以及心肌梗塞偵測等12 導層信號處理引擎。而腦波屬於相當微弱且易受干擾的信號,因此本計畫將提出使用於64 通道腦波信號處理器之獨立成分分析系統。在擴散光學斷層掃描的部分,則是提出一種新式的光學掃描方式,透過此新式的掃描架構是一種可以達到在人體上移動偵測,並整合移動過程中掃描到的圖像進行綜合判讀的技術。而為達到極低功率消耗的目標,本計畫將對系統各部份進行功耗分析,並利用Cadence 工具及研發團隊自主設計之極低功率元件庫使晶片達到最低功耗的特性有效提升前端生醫感測系統的可攜性及可穿戴性,並且使用高階封裝技術技術有效減少晶片體積、改善可靠度及測試品質、並達到異質整合成果。最後,本計畫所產出的低功耗多核生醫信號處理系統晶片平台將與其他子計畫進行整合,並完成整體系統架構,並進行驗證。 A dynamic energy-aware multiprocessor SoC platform biomedical signal computing based on next generation intelligent ICU application will be proposed in this proposal. It includes three key technology: 12-lead Electrocardiography (ECG) processor, 64-channels Electroencephalography (EEG) processor, and Diffuse Optical Tomography (DOT) bio-image processor.1. The ECG processor will focus on heart rate variability (HRV) analysis and myocardial infarction (MI) detection.2. Since the brain waves are very weak and sensitive, the 64-channels independent component analysis engine is proposed in this proposal. It will be the key technology in the EEG processor.3. In the DOT engine part, we propose a new optical tomography technology to achieve scanning human body dynamically and determining the image scanned.4. To achieve low power consumption, this proposal will analyze the power of separate part. Then using the Cadence tool and the library our P&D team made to make the lowest power consumed chip. By reaching the feature mentioned, it can highly promote the portability and wearablity of whole system. And by using the high level package technology, it can reduce the chip volume and improve the reliability of testing, and then achieve the goal of heterogeneous integration.Finally, the multi-core low power biomedical chip produced in this project will integrate with other project and finish the whole system architecture, and then we will verify its function. |
官方說明文件#: | NSC100-2220-E009-054 |
URI: | http://hdl.handle.net/11536/99548 https://www.grb.gov.tw/search/planDetail?id=2312853&docId=361610 |
Appears in Collections: | Research Plans |