量子線矽、鍺、砷化鎵奈米CMOS元件內電荷傳輸模擬與可靠性

Abstract

當 CMOS 元件微縮至22 奈米以下，無論在元件結構、材料及傳輸物理方面均將產生重大變 化；(i)元件結構將由目前之平面式閘極改為圍繞式閘極(例如 FinFET 或nanowire FET)，在此種 元件內，通道電荷在兩個方向將受到量子侷限而具備量子線性質，(ii)通道材料將包括strained Si, Ge, GaAs 以提升電荷傳輸速度，(iii)當通道長度小於22 奈米，電荷傳輸將呈現非平衡傳輸 (non-equilibrium transport)特性，傳統之drift-diffusion 觀念將不再適用。而在可靠性方面， bias-temperature-instability (BTI)及元件雜訊(random telegraph noise (RTN))為奈米元件兩項主要可 靠性議題，由於此兩種物理機制均與通道內電流之percolation path 有關，當元件結構由平面式改 為量子線元件，由於具有不同的percolation effect，上述兩項物理機制亦將有所改變。 面對以上重大變化，在電荷傳輸方面，吾人將發展 Si, Ge, GaAs 量子線蒙地卡羅模擬。模擬 程式將包括三個部份；(i)一維電子(和電洞)能帶計算，(ii) 一維電子(和電洞)之載子碰撞機制及蒙 地卡羅模擬程式及(iii)通道方向電場計算。有別於一般量子線蒙地卡羅模擬，在本計劃內吾人將 發展一適合22 奈米以下量子線模擬方法，以研究元件內之非平衡傳輸。在量測方面，吾人將量 測FinFET 之電荷傳輸參數(例如back-scattering 係數)，並和理論比對。而在可靠性方面，吾人將 利用特殊組裝電路量測FinFET 元件內之BTI 與RTN，並藉由數值模擬，發展電荷捕捉/釋放之隨 機程序模型，並研究平面式與圍繞式閘極元件內此兩種可靠性物理機制之差異。

As CMOS devices are scaled beyond 22nm, drastic changes and new challenges are expected in device structures, channel materials and carrier transport and reliability physics. (i) In device structures, conventional planar gates will be replaced by surrounding gates such as FinFETs or nanowire FETs. In FinFET devices, carriers are quantum-mechanically confined in two directions and thus possess quantum-wire transport properties. (ii) To further improve device performance, advanced channel materials, for example, strained Si, Ge or GaAs, will be implemented. (iii) In ultra-short channel CMOS, carriers move in a non-equilibrium condition with an electric field. Conventional drift and diffusion concepts are no longer valid. Instead, new transport phenomena such as quasi-ballistic motion or velocity overshoot will become prominent in nano-scale CMOS. In transport simulation, we will develop a quantum-wire Monte Carlo simulation including Si, Ge and GaAs three materials. We will develop a particular simulation flow, which is suitable for quasi-ballistic transport simulation in 22nm FinFET devices and beyond. Our simulation flow features three ingredients, quantum-wire band-structure solver (coupled 2D Poisson and Schrodinger Eqs.), Monte Carlo simulation including one-dimensional scattering processes and a Poisson solver for an electric field in the channel. All of the three parts will be solved self-consistently in order for a device biased in saturation region. In addition, we will characterize transport parameters in FinFET CMOS such as back-scattering coefficient and ballistic injection efficiency and compare with our simulation. With respect to reliability in quantum structure CMOS, our study will be focused on bias temperature instability (BTI) and random telegraph noise (RTN) in FinFET devices. We will measure individual carrier captures and emissions in gate dielectric during BTI stress and in relaxation. A stochastic model for carrier trapping/detrapping will be developed. We will also perform numerical device simulation to analyze current-path percolation effects on RTN and BTI. We will explore and compare the characteristics and physical mechanisms of these two reliability issues in conventional planar gate FETs and surrounding gate FETs with quantum structures.