THz醫學影像系統及元件---子計畫四：Terahertz CMOS射頻陣列接收機(I)

Abstract

本子計畫將透過CMOS 射頻偵測器陣列系統晶片的研究與設計，提升Terahertz 接收器系統的轉換增益、動態範圍與研究Terahertz 射頻陣列偵測方式。研究的主題主 要分為四個部分：首先我們將考量現今半導體製程，搭配電路網路的物理可實現性， 找出任意網路的Terahertz CMOS 電晶體電路的運作極限及設計取捨。由於Terahertz 的CMOS 電晶體模型係該高頻電路設計的基礎，我們同時會設計出電晶體測試晶片與校 準晶片，來精確的進行Terahertz CMOS 電晶體建模，作為後續電路設計的依據。 整個Terahertz 陣列接收器有兩個關鍵電路，分別是低雜訊放大器與射頻混頻 器，這兩個關鍵電路會決定整個系統的最高運作頻率。第二部分利用電路物理可實性 理論與電晶體建模的研究結果，重新研究關鍵電路。在低雜訊放大器的部分，考量阻 抗匹配限制條件進行雜訊指數之最佳化，搭配物理可實現性任意網路合成，提高低雜 訊放大器於Terahertz 之效能。射頻混頻器的研究重點將在於提高轉換增益、降低電 路雜訊，以及線性度。 第三部分是Terahertz 射頻偵測系統EDA 流程的研究與設計，這一部分的研究主 要任務係負責銜接電路層級及系統層級的Terahertz 晶片設計，設計常用的類比及射 頻佈局pcell，將該pcell 進行對等的電磁模擬以及多模擬層級的電路建模，並修改 extraction rule，使其與晶圓廠所提供的EDA 環境進行整合，加快Terahertz 晶片系 統的設計及驗證效率。第四部分是Terahertz 可延展偵測器陣列系統晶片的研究與設 計，分別針對同調以及非同調偵測器，提出幾種可行的陣列偵測器架構；配合關鍵電 路的研究與EDA 流程，評估在所使用的製程下最合適的系統架構。 所有的測試、電路及系統晶片將以65 奈米或以下CMOS 製程製造。我們將透過電 路理論分析、電路設計、佈局、佈局後電路合併電磁模擬、系統層級電路合併電磁模 擬，最後完成可製造性驗證，再透過晶圓廠大學計畫，亦或國家晶片系統設計中心進 行下線。晶片將會透過封裝、量測，驗證我們的研究成果。

This project studies and designs a CMOS terahertz RF detector array integrated system. Different terahertz array detection systems will be compared, and the design goal is to achieve a high system conversion gain and dynamic range. Conventional transistor network synthesis assumes perfect metal conductivity. At terahertz, this assumption is far from reality. We will consider physical reliability of passive network based on current semiconductor process, and derive the realizable maximum gain frequency of terahertz CMOS transistor amplifiers. Theoretic studies will help clarify circuit design tradeoffs in terahertz regime. Test chips of CMOS transistors, and the corresponding parasitic calibration chip will also be fabricated. These chips will accomplish terahertz transistor models, which will later be used in circuit design. The low noise amplifier (LNA) and the RF mixer are the key circuits of our systems. They set the upper bounds on the system operating frequency and its performance. In the second part, we will utilize the results from physical realizable network theory and terahertz transistor modeling to analyze both LNA and mixer. In the design of LNA, noise optimization will carried with constraints on input impedance matching, and arbitrary physical realizable network. This will improve terahertz LNA performance. Research focuses for RF mixer will be on improving circuit conversion gain, lowering noise figure and increasing linearity. In the third part, we will custom build EDA design flow for terahertz RF detector systems. The appropriate design environment can efficiently bridge terahertz IC design at circuit and system levels. We will firstly design layout pcell for commonly-used analog and RF circuits, make circuit models at different simulation accuracies, and integrate them into the extraction rules provided by the foundry. These efforts will make terahertz system design/verification effectively and efficiently. In the last part, we study and design terahertz scalable detector array system IC. We will propose several non-coherent and coherent detector architectures, compare their performances based on circuit studies, and implement the one with best overall performance. All integrated circuits will be fabricated using a 65nm (or narrower) CMOS process. Designs will be verified through circuit analysis, computer simulations, layout/post-layout simulations, system-level EM/SPICE co-simulations, layout versus schematic checks, and design rule checks. Chips will be packaged and measured to verify our theories and designs.