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Interface Engineering for High-Performance Top-Gated MoS2 Field-Effect Transistors

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dc.citation.epage6261en_US
dc.citation.issue36en_US
dc.citation.spage6255en_US
dc.citation.volume26en_US
dc.citation.woscount5
dc.contributor.authorZou, Xumingen_US
dc.contributor.authorWang, Jinglien_US
dc.contributor.authorChiu, Chung-Huaen_US
dc.contributor.authorWu, Yunen_US
dc.contributor.authorXiao, Xianghengen_US
dc.contributor.authorJiang, Changzhongen_US
dc.contributor.authorWu, Wen-Weien_US
dc.contributor.authorMai, Liqiangen_US
dc.contributor.authorChen, Tangshengen_US
dc.contributor.authorLi, Jinchaien_US
dc.contributor.authorHo, Johnny C.en_US
dc.contributor.authorLiao, Leien_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.date.accessioned2014-12-08T15:36:47Z
dc.date.available2014-12-08T15:36:47Z
dc.date.issued2014-09-24en_US
dc.description.abstractExperimental evidence of the optimized interface engineering effects in MoS2 transistors is demonstrated. The MoS2/Y2O3/HfO2 stack offers excellent interface control. Results show that HfO2 layer can be scaled down to 9 nm, yet achieving a near-ideal sub-threshold slope (65 mv/dec) and the highest saturation current (526 mu A/mu m) of any MoS2 transistor reported to date.en_US
dc.identifier.doi10.1002/adma.201402008en_US
dc.identifier.issn0935-9648en_US
dc.identifier.journalADVANCED MATERIALSen_US
dc.identifier.urihttp://dx.doi.org/10.1002/adma.201402008en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/25173
dc.identifier.wosnumberWOS:000342622700005
dc.language.isoen_USen_US
dc.subjectMoS2en_US
dc.subjecttop-gateden_US
dc.subjecttransistorsen_US
dc.subjectinterface engineeringen_US
dc.subjecttwo-dimensional materialsen_US
dc.titleInterface Engineering for High-Performance Top-Gated MoS2 Field-Effect Transistorsen_US
dc.typeArticleen_US

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