On the design of selective coefficient DCT module

Abstract

In this transactions letter, an innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation, Having these features, the selective coefficient DCT core will fit for various area/speed requirements, It can save the transposition delay to simplify the computation how of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient.