On the design of selective coefficient DCT module
| dc.citation.epage | 146 | en_US |
| dc.citation.issue | 2 | en_US |
| dc.citation.spage | 143 | en_US |
| dc.citation.volume | 8 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | Lu, CY | en_US |
| dc.contributor.author | Wen, KA | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:49:13Z | |
| dc.date.available | 2014-12-08T15:49:13Z | |
| dc.date.issued | 1998-04-01 | en_US |
| dc.description.abstract | In this transactions letter, an innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation, Having these features, the selective coefficient DCT core will fit for various area/speed requirements, It can save the transposition delay to simplify the computation how of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient. | en_US |
| dc.identifier.doi | 10.1109/76.664099 | en_US |
| dc.identifier.issn | 1051-8215 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/76.664099 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/32707 | |
| dc.identifier.wosnumber | WOS:000072884000007 | |
| dc.language.iso | en_US | en_US |
| dc.subject | DCT | en_US |
| dc.subject | selective coefficient | en_US |
| dc.subject | 2-D DCT | en_US |
| dc.title | On the design of selective coefficient DCT module | en_US |
| dc.type | Article | en_US |