Low power parallel Huffman decoding
| dc.citation.epage | 241 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 240 | en_US |
| dc.citation.volume | 34 | en_US |
| dc.citation.woscount | 7 | |
| dc.contributor.author | Lin, CH | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:49:21Z | |
| dc.date.available | 2014-12-08T15:49:21Z | |
| dc.date.issued | 1998-02-05 | en_US |
| dc.description.abstract | A low power design technique for a parallel Huffman decoder is presented. According to the length of the incoming Huffman codeword, the proposed strategy makes the barrel shifter in the parallel Huffman decoder turn off the unnecessary shifting bits to reduce power dissipation. The result of a SPICE simulation indicates that up to 50 percent power reduction in the barrel shifter may be achieved with the proposed technique. | en_US |
| dc.identifier.issn | 0013-5194 | en_US |
| dc.identifier.journal | ELECTRONICS LETTERS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/32794 | |
| dc.identifier.wosnumber | WOS:000072152200011 | |
| dc.language.iso | en_US | en_US |
| dc.title | Low power parallel Huffman decoding | en_US |
| dc.type | Article | en_US |